AOD403/aoi403 30v p-channel mosfet general description product summary v ds i d (at v gs = -20v) -70a r ds(on) (at v gs = -20v) < 6.2m w r ds(on) (at v gs = -10v) < 8m w 100% uis tested 100% r g tested symbol v ds the AOD403/aoi403 uses advanced trench technology to provide excellent r ds(on) , low gate charge and low gate resistance. with the excellent thermal resistance o f the dpak/ipak package, this device is well suited for h igh current load applications. v maximum units parameter absolute maximum ratings t a =25c unless otherwise noted -30v drain-source voltage -30 to252 dpak top view bottom view g s d g s d g ds g g d d s s top view bottom view to251a ipak v ds v gs i dm i as , i ar e as , e ar t j , t stg symbol t 10s steady-state steady-state r q jc maximum junction-to-case c/w c/w maximum junction-to-ambient a d 0.9 50 1.6 w power dissipation a p dsm w t a =70c 90 1.6 t a =25c -55 t c =25c t c =100c power dissipation b p d continuous drain current 125 -15 -50 a t a =25c i dsm a t a =70c -200 pulsed drain current c continuous drain current g i d -70 v v 25 gate-source voltage drain-source voltage -30 avalanche energy l=0.1mh c mj avalanche current c -12 a c thermal characteristics units maximum junction-to-ambient a c/w r q ja 16 41 20 parameter typ max t c =25c 2.5 45 t c =100c junction and storage temperature range -55 to 175 rev 8: may 2011 www.aosmd.com page 1 of 6
AOD403/aoi403 symbol min typ max units bv dss -30 v v ds =-30v, v gs =0v -1 t j =55c -5 i gss 100 na v gs(th) gate threshold voltage -1.5 -2.5 -3.5 v i d(on) -200 a 5.1 6.2 t j =125c 7.6 9.2 g fs 42 s v sd -0.7 -1 v i s -70 a c iss 2310 2890 3500 pf c oss 410 585 760 pf c rss 280 470 660 pf r g 1.9 3.8 5.7 w q 40 51 61 nc v gs =0v, v ds =-15v, f=1mhz switching parameters electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions drain-source breakdown voltage i d =-250 m a, v gs =0v v gs =-10v, v ds =-5v v gs =-20v, i d =-20a forward transconductance diode forward voltage v gs =-10v, i d =-20a to252 i s =-1a,v gs =0v v ds =-5v, i d =-20a on state drain current static drain-source on-resistance vgs=-10v, id=-20a to251a i dss m a v ds =v gs i d =-250 m a v ds =0v, v gs = 25v zero gate voltage drain current gate-body leakage current m w to252 6.2 8 m w v gs =-20v, i d =-20a to251a gate resistance v gs =0v, v ds =0v, f=1mhz total gate charge reverse transfer capacitance maximum body-diode continuous current g input capacitance output capacitance dynamic parameters r ds(on) m w m w 5.6 6.7 6.7 8.5 q g 40 51 61 nc q gs 10 12 14 nc q gd 10 16 22 nc t d(on) 16 ns t r 12 ns t d(off) 45 ns t f 22 ns t rr 14 18 22 ns q rr 9 11 13 nc this product has been designed and qualified for th e consumer market. applications or uses as critical components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. i f =-20a, di/dt=100a/ m s body diode reverse recovery time turn-off fall time total gate charge v gs =-10v, v ds =-15v, i d =-20a gate source charge gate drain charge v gs =-10v, v ds =-15v, r l =0.75 w , r gen =3 w turn-off delaytime body diode reverse recovery charge i f =-20a, di/dt=100a/ m s turn-on delaytime turn-on rise time a. the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air environ ment with t a =25 c. the power dissipation p dsm is based on r q ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user's specific board design, and the maximu m temperature of 175 c may be used if the pcb allows it. b. the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and i s more useful in setting the upper dissipation limit for cases where additional heatsi nking is used. c. repetitive rating, pulse width limited by juncti on temperature t j(max) =175 c. ratings are based on low frequency and duty cycl es to keep initial t j =25 c. d. the r q ja is the sum of the thermal impedence from junction t o case r q jc and case to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-case t hermal impedence which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of t j(max) =175 c. the soa curve provides a single pulse rating. g. the maximum current rating is package limited. h. these tests are performed with the device mounte d on 1 in 2 fr-4 board with 2oz. copper, in a still air environ ment with t a =25 c. rev 8: may 2011 www.aosmd.com page 2 of 6
AOD403/aoi403 typical electrical and thermal characteristics 17 52 10 0 18 0 20 40 60 80 100 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 -i d (a) -v gs (volts) figure 2: transfer characteristics (note e) 2 4 6 8 10 0 5 10 15 20 25 30 r ds(on) (m w ww w ) -i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) 0.8 1 1.2 1.4 1.6 1.8 0 25 50 75 100 125 150 175 200 normalized on-resistance temperature (c) figure 4: on-resistance vs. junction temperature (note e) v gs =-10v i d =-20a v gs =-20v i d =-20a 25 c 125 c v ds =-5v v gs =-10v v gs =-20v 0 20 40 60 80 100 0 1 2 3 4 5 -i d (a) -v ds (volts) fig 1: on-region characteristics (note e) v gs =-4v -4.5v -6v -10v -5v 18 40 gate voltage (note e) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 1.0e+02 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -i s (a) -v sd (volts) figure 6: body-diode characteristics (note e) 25 c 125 c (note e) 0 5 10 15 20 0 5 10 15 20 r ds(on) (m w ww w ) -v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) i d =-20a 25 c 125 c rev 8: may 2011 www.aosmd.com page 3 of 6
AOD403/aoi403 typical electrical and thermal characteristics 0 2 4 6 8 10 0 10 20 30 40 50 60 -v gs (volts) q g (nc) figure 7: gate-charge characteristics 0 1000 2000 3000 4000 5000 0 5 10 15 20 25 30 capacitance (pf) -v ds (volts) figure 8: capacitance characteristics c iss 0 80 160 240 320 400 0.0001 0.001 0.01 0.1 1 10 power (w) pulse width (s) figure 10: single pulse power rating junction - to - c oss c rss v ds =-15v i d =-20a t j(max) =175 c t c =25 c 10 m s 0.0 0.1 1.0 10.0 100.0 1000.0 0.01 0.1 1 10 100 -i d (amps) -v ds (volts) figure 9: maximum forward biased 10 m s 10ms 1ms dc r ds(on) limited t j(max) =175 c t c =25 c 100 m s 40 figure 10: single pulse power rating junction - to - case (note f) 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 z q qq q jc normalized transient thermal resistance pulse width (s) figure 11: normalized maximum transient thermal imp edance (note f) single pulse d=t on /t t j,pk =t c +p dm .z q jc .r q jc t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse figure 9: maximum forward biased safe operating area (note f) r q jc =1.6 c/w rev 8: may 2011 www.aosmd.com page 4 of 6
AOD403/aoi403 typical electrical and thermal characteristics 0 18 0 30 60 90 120 150 0 25 50 75 100 125 150 175 power dissipation (w) t case (c) figure 13: power de-rating (note f) 0 10 20 30 40 50 60 70 80 0 25 50 75 100 125 150 175 current rating i d (a) t case ( c) 1 10 100 1000 10000 0.00001 0.001 0.1 10 1000 power (w) pulse width (s) figure 15: single pulse power rating junction - to - t a =25 c 10.0 100.0 1000.0 1 10 100 1000 -i ar (a) peak avalanche current time in avalanche, t a (ms) figure 12: single pulse avalanche capability (note c) t a =25 c t a =150 c t a =100 c t a =125 c 18 40 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 z q qq q ja normalized transient thermal resistance pulse width (s) figure 16: normalized maximum transient thermal imp edance (note h) single pulse d=t on /t t j,pk =t a +p dm .z q ja .r q ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse t case ( c) figure 14: current de-rating (note f) figure 15: single pulse power rating junction - to - ambient (note h) r q ja =50 c/w rev 8: may 2011 www.aosmd.com page 5 of 6
AOD403/aoi403 vdc ig vds dut vdc vgs vgs qg qgs qgd charge gate charge test circuit & waveform - + - + -10v id vds unclamped inductive switching (uis) test circuit & waveforms vds l 2 e = 1/2 li ar ar vdc dut vdd vgs vds vgs rl rg resistive switching test circuit & waveforms - + vgs vds t t t t t t 90% 10% r on d(off) f off d(on) vdd vgs id vgs rg dut vdc vgs id vgs - + bv dss i ar ig vgs - + vdc dut l vgs isd diode recovery test circuit & waveforms vds - vds + di/dt rm rr vdd vdd q = - idt t rr -isd -vds f -i -i rev 8: may 2011 www.aosmd.com page 6 of 6
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